Raspberry Pi /RP2350 /DMA /CH6_CTRL_TRIG

DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

0 (SIZE_BYTE): undefined

1 (SIZE_HALFWORD): undefined

2 (SIZE_WORD): undefined

If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

Generally this should be disabled for peripheral-to-memory transfers.

If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.

If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.

If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

Generally this should be disabled for memory-to-peripheral transfers.

If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.

If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.

0 (RING_NONE): undefined

Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).

Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.

Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ

0 (PIO0_TX0): Select PIO0’s TX FIFO 0 as TREQ

1 (PIO0_TX1): Select PIO0’s TX FIFO 1 as TREQ

2 (PIO0_TX2): Select PIO0’s TX FIFO 2 as TREQ

3 (PIO0_TX3): Select PIO0’s TX FIFO 3 as TREQ

4 (PIO0_RX0): Select PIO0’s RX FIFO 0 as TREQ

5 (PIO0_RX1): Select PIO0’s RX FIFO 1 as TREQ

6 (PIO0_RX2): Select PIO0’s RX FIFO 2 as TREQ

7 (PIO0_RX3): Select PIO0’s RX FIFO 3 as TREQ

8 (PIO1_TX0): Select PIO1’s TX FIFO 0 as TREQ

9 (PIO1_TX1): Select PIO1’s TX FIFO 1 as TREQ

10 (PIO1_TX2): Select PIO1’s TX FIFO 2 as TREQ

11 (PIO1_TX3): Select PIO1’s TX FIFO 3 as TREQ

12 (PIO1_RX0): Select PIO1’s RX FIFO 0 as TREQ

13 (PIO1_RX1): Select PIO1’s RX FIFO 1 as TREQ

14 (PIO1_RX2): Select PIO1’s RX FIFO 2 as TREQ

15 (PIO1_RX3): Select PIO1’s RX FIFO 3 as TREQ

16 (PIO2_TX0): Select PIO2’s TX FIFO 0 as TREQ

17 (PIO2_TX1): Select PIO2’s TX FIFO 1 as TREQ

18 (PIO2_TX2): Select PIO2’s TX FIFO 2 as TREQ

19 (PIO2_TX3): Select PIO2’s TX FIFO 3 as TREQ

20 (PIO2_RX0): Select PIO2’s RX FIFO 0 as TREQ

21 (PIO2_RX1): Select PIO2’s RX FIFO 1 as TREQ

22 (PIO2_RX2): Select PIO2’s RX FIFO 2 as TREQ

23 (PIO2_RX3): Select PIO2’s RX FIFO 3 as TREQ

24 (SPI0_TX): Select SPI0’s TX FIFO as TREQ

25 (SPI0_RX): Select SPI0’s RX FIFO as TREQ

26 (SPI1_TX): Select SPI1’s TX FIFO as TREQ

27 (SPI1_RX): Select SPI1’s RX FIFO as TREQ

28 (UART0_TX): Select UART0’s TX FIFO as TREQ

29 (UART0_RX): Select UART0’s RX FIFO as TREQ

30 (UART1_TX): Select UART1’s TX FIFO as TREQ

31 (UART1_RX): Select UART1’s RX FIFO as TREQ

32 (PWM_WRAP0): Select PWM Counter 0’s Wrap Value as TREQ

33 (PWM_WRAP1): Select PWM Counter 1’s Wrap Value as TREQ

34 (PWM_WRAP2): Select PWM Counter 2’s Wrap Value as TREQ

35 (PWM_WRAP3): Select PWM Counter 3’s Wrap Value as TREQ

36 (PWM_WRAP4): Select PWM Counter 4’s Wrap Value as TREQ

37 (PWM_WRAP5): Select PWM Counter 5’s Wrap Value as TREQ

38 (PWM_WRAP6): Select PWM Counter 6’s Wrap Value as TREQ

39 (PWM_WRAP7): Select PWM Counter 7’s Wrap Value as TREQ

40 (PWM_WRAP8): Select PWM Counter 8’s Wrap Value as TREQ

41 (PWM_WRAP9): Select PWM Counter 9’s Wrap Value as TREQ

42 (PWM_WRAP10): Select PWM Counter 0’s Wrap Value as TREQ

43 (PWM_WRAP11): Select PWM Counter 1’s Wrap Value as TREQ

44 (I2C0_TX): Select I2C0’s TX FIFO as TREQ

45 (I2C0_RX): Select I2C0’s RX FIFO as TREQ

46 (I2C1_TX): Select I2C1’s TX FIFO as TREQ

47 (I2C1_RX): Select I2C1’s RX FIFO as TREQ

48 (ADC): Select the ADC as TREQ

49 (XIP_STREAM): Select the XIP Streaming FIFO as TREQ

50 (XIP_QMITX): Select XIP_QMITX as TREQ

51 (XIP_QMIRX): Select XIP_QMIRX as TREQ

52 (HSTX): Select HSTX as TREQ

53 (CORESIGHT): Select CORESIGHT as TREQ

54 (SHA256): Select SHA256 as TREQ

59 (TIMER0): Select Timer 0 as TREQ

60 (TIMER1): Select Timer 1 as TREQ

61 (TIMER2): Select Timer 2 as TREQ (Optional)

62 (TIMER3): Select Timer 3 as TREQ (Optional)

63 (PERMANENT): Permanent request, for unpaced transfers.

In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.

Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

This allows checksum to be enabled or disabled on a per-control- block basis.

This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.

If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.